1. Field of the Invention
The invention relates to the field of integrated circuit interconnections and, in particular, to structures and methods for vertically stacking chips for increased volume density without increased footprint.
2. Description of the Related Art
Modern electronic devices, such as computers and the like, typically include integrated circuits encapsulated in packages generally referred to generically as xe2x80x9cchipsxe2x80x9d. Chips are generally planar structures and typically include a plurality of conducting pads disposed as surface contacts about a surface of the chip and/or xe2x80x9cpinsxe2x80x9d along an edge thereof. The conducting pads generally interconnect to a plurality of interconnecting conductive traces that extend from the pads to the electronic devices within the chip and allow interconnection of the electronic devices to external circuits to allow a system level circuit.
With advances in semiconductor device processing has come a continuing increase in device count and density within chips and this has driven a corresponding increase in the count and density of the external conducting pads. Current technology places a limit on how small external contacts can be made and how closely they can be placed adjacent one another while still maintaining circuit integrity. Limits are imposed both by the limitations of machinery to form ever smaller conductive elements and the reduction in production yield as the limits are pushed.
An additional concern is an overall system level consideration of packaging. As previously mentioned, chips are generally planar structures with relatively thin, flat profile. A common practice has been to interconnect chips on another generally planar support structure often referred to as a xe2x80x9cmother boardxe2x80x9d. However, the desire to provide the capability of integrated circuits to relatively small devices limits the extent to which multiple chips can be laterally interconnected while still fitting within the device. In addition, lateral extension and interconnection of chips tends to lead to relatively long interconnects between chips and thus between circuit components thus introducing propagation delays that can limit the practical speed of operation of the system level circuits.
From the foregoing, it can be appreciated that there is an ongoing need for structures and methods for interconnecting chips to increase circuit density without increasing the chip footprint and with minimal increase in interconnection length.
The aforementioned needs are satisfied by the invention which in one aspect is various structures and methods for interconnecting a plurality of generally planar chips in a vertical stack such that the stack chips define interstitial spaces that provide clearance for additional chips to be placed therein. The various structures and methods include the aspect that the total footprint of the stack does not exceed the footprint of the single largest component chip.
A certain aspect of the invention is a chip stack of a preformed support structure vertically interconnecting a first chip to a second chip with a third chip interposed therebetween wherein the support structure comprises a rigid annular housing defining an opening adapted to provide clearance for the third chip and a plurality of conductor cavities disposed about the periphery of the housing and extending between a first face and an opposite second face of the housing and a plurality of conductive elements positioned within the conductor cavities such that a portion of each conductive element extends slightly beyond the first and second faces of the housing so as to interconnect the first and second chips and such that each of the conductive element extends substantially flush with the edges of the conductor cavities on the first and second faces of the housing so as to substantially fill the corresponding conductor cavity. A particular aspect therein is wherein the conductor cavities of the support structure are substantially rectangular in horizontal cross-section or more particularly wherein the conductor cavities of the support structure are substantially square in horizontal cross-section.
Other aspects of the invention are wherein walls of the conductor cavities are substantially parallel to other conductor cavity walls along their adjacency to the adjacent conductor cavities and/or wherein the conductor cavities define first opposing walls facing adjacent conductor cavities and second opposing walls between the first walls wherein the first walls are generally planar and parallel to the first walls of adjacent conductor cavities and wherein the second walls are generally convexly curved.
The invention also includes the aspects of a preformed support structure for vertically interconnecting a first chip to a second chip with a third chip interposed therebetween wherein the support structure comprises a rigid annular housing defining an opening adapted to provide clearance for the third chip and a plurality of conductor cavities disposed about the periphery of the housing and extending between a first face and an opposite second face of the housing and a plurality of conductive elements positioned within the conductor cavities such that a portion of each conductive element extends slightly beyond the first and second faces of the housing and such that each of the conductive element extends substantially flush with the edges of the conductor cavities on the first and second faces of the housing so as to substantially fill the corresponding conductor cavity. A particular aspect therein is wherein the conductor cavities of the support structure are substantially rectangular in horizontal cross-section and more particularly wherein the conductor cavities of the support structure are substantially square in horizontal cross-section.
The invention further includes the aspect wherein walls of the conductor cavities are substantially parallel to other conductor cavity walls along their adjacency to the adjacent conductor cavities and wherein the conductor cavities define first opposing walls facing adjacent conductor cavities and second opposing walls between the first walls wherein the first walls are generally planar and parallel to the first walls of adjacent conductor cavities and wherein the second walls are generally convexly curved.
The invention is also a method of interconnecting chips having surface contacts comprising forming a generally annular support structure with a plurality of conductor cavities extending between opposite faces of the support structure and aligned with the surface contacts, filling the conductor cavities with conductive material such that the conductive material substantially fills the conductor cavities and extends slightly beyond the opposite faces of the support structure, placing chips on the support structure such that the surface contacts are adjacent and aligned with the conductor cavities so as to form a stack of the chips and the support structure, and processing the stack so as to induce the conductive material to connect to the surface contacts.
Yet another aspect of the invention is a chip stack of at least a first, a second, and a third chip and conductive interconnecting structures of at least a first size and a second smaller size interconnecting the chips wherein the third chip has a smaller footprint than either of the first or second chips and wherein the first conductive structures interconnect the first and second chips so as to define an interstitial space therebetween and the third chip is connected to at least one of the first and the second chips via the second conductive structures and is positioned within the interstitial space such that the vertical extent of the first conductive support structures is greater than the combined vertical extent of the third chip and the second conductive support structures. Particularly therein, the invention includes wherein the third chip is connected to one of the first or the second chips via the second conductive structures.
An additional aspect of the invention is a chip stack of at least a first, a second, and a third chip and conductive interconnecting structures of a first size interconnecting the first and second chips to the third chip wherein the third chip has a larger footprint than either of the first or second chips and further comprising second conductive support structures connected to the third chip such that the vertical extent of the second conductive support structures is greater than the combined vertical extent of either the first or second chips and the associated first conductive support structures.
These and other objects and advantages of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings.